1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and particularly to a semiconductor device comprising a bipolar transistor.
2. Related Art
In recent years, in a semiconductor device used at a high frequency is strongly required improvement in frequency characteristics such as a current gain bandwidth product fT and a maximum oscillation frequency fmax or improvement in noise characteristics such as a noise factor NF. Further, a high break down voltage (VCEO) between a collector and an emitter is required in harmony with actual use of high power supply.
FIG. 9 shows an NPN bipolar transistor according to a conventional technique. An N-type collector layer 902 made of a silicon layer is formed on an N-type silicon substrate 901. Further, an element isolating region 903 made of an oxide film is formed in a region other than element forming portions by a LOCOS (Local Oxidation of Silicon) process, and a thin oxide film 904 is formed on part of the N-type collector layer 902. Further, a base leading-out region 905 made of polycrystalline silicon is formed on the oxide film 904 on the N-type collector layer 902 and the element isolating region 903. A P-type base layer 906 made of a SiGe layer is formed on the base leading-out region 905 and the N-type collector layer 902. It is also possible to form a P-type base layer made of a silicon layer without adding Ge.
An N-type emitter layer 907 is selectively formed in a surface region of the P-type base layer 906 on the N-type collector layer 902. Interlayer dielectrics 908 and 909 provided with an opening for contact hole are formed on the P-type base layer 906, and an emitter leading-out region 910 made of polycrystalline silicon is formed on the N-type emitter layer 907. The emitter leading-out region 910 and the P-type base layer 906 are electrically insulated from each other by the interlayer dielectric 908.
Furthermore, an emitter electrode 911 and a base electrode 912 are formed on the emitter leading-out region 910 and the base leading-out region 905 by embedding a conductive material in the openings for contact hole.
Next, FIG. 10A to FIG. 12 show a method for manufacturing the NPN bipolar transistor according to the conventional technique. As shown in FIG. 10A, the N-type collector layer 902 made of a silicon layer is formed on the N-type silicon substrate 901 by epitaxially growing the silicon while adding N-type impurities. Subsequently, the element isolating region 903 made of an oxide film is formed in a region other than element forming portions by the LOCOS (Local Oxidation of Silicon) process, and the thin oxide film 904 is formed on the N-type collector layer 902.
Next, as shown in FIG. 10B, a polycrystalline silicon layer 913 is formed on the element isolating region 903 and the oxide film 904. Subsequently, the polycrystalline silicon layer 913 and the oxide film 904 are etched such that part of the N-type collector layer 902 is exposed. Etching of the oxide film 904 is performed by wet-etching. Next, P-type impurities are ion-implanted into the polycrystalline silicon layer 913 to form the base leading-out region 905.
Next, as shown in FIG. 10C, the P-type base layer 906 made of a silicon layer is formed on the base leading-out region 905 and the N-type collector layer 902 by epitaxially growing the silicon while adding the p-type impurities. Here, the P-type base layer made of a SiGe layer may be formed by epitaxially growing the silicon while adding the P-type impurities and Ge.
Next, as shown in FIG. 11A, the interlayer dielectric 908 is formed on the P-type base layer 906, and the interlayer dielectric 908 is etched such that part of the P-type base layer 906 formed on the N-type collector layer 902 is exposed. Subsequently, a polycrystalline silicon layer 914 is formed on the interlayer dielectric 908 and the exposed P-type base layer 906, and the emitter leading-out region 910 is formed and the N-type emitter layer 907 is formed in part of the surface region of the P-type base layer 906 by ion-implanting the N-type impurities into the polycrystalline silicon layer 914 and performing thermal processing.
Next, as shown in FIG. 11B, the interlayer dielectric 909 is formed on the base leading-out region 905 and the emitter leading-out region 910. The base electrode 912 and the emitter electrode 911 connected to the base leading-out region 905 and the emitter leading-out region 910 respectively are formed by forming openings such that part of the base leading-out region 905 and part of the emitter leading-out region 910 are exposed, and embedding a conductive material in the openings. Japanese Patent Application Laid-Open No. 11-233523 is known as one example of the semiconductor device comprising such an NPN bipolar transistor.
In FIG. 10C, in the case of forming the P-type base layer 906 by epitaxial growth, thermal processing at about 600° C. is generally performed. At this time, the P-type impurities ion-implanted into the base leading-out region 905 are scattered to the neighboring P-type base layer 906 as shown by arrows in FIG. 10C, and an abnormal profile of the P-type impurities is formed near the interface between the P-type base layer 906 and the N-type collector layer 902.
FIG. 12 shows an impurity concentration across B–B′ section, and this abnormal profile of the P-type impurities is called a P-type auto-doped layer 1301. Since the P-type auto-doped layer 1301 is generated so that a width of the base layer is substantially widened, there is a problem that a base traveling time of carriers is increased and the frequency characteristics are deteriorated. This P-type auto-doped layer 1301 is mainly formed by the thermal processing at the time of forming the P-type base layer 906 by epitaxial growth, but can be formed by thermal processing in other step. Further, even when the P-type base layer 906 is not formed by epitaxial growth, the layer may be formed by other thermal process.
Further, in a semiconductor device having an N-type collector layer which does not have a relatively low concentration, even when the P-type impurities are diffused near the interface between the P-type base layer and the N-type collector layer, the P-type auto-doped layer is not formed substantially because the N-type collector layer does not have the relatively low concentration. Here, the relatively low concentration refers to, for example, 3×1016 cm−3.
Therefore, there is a problem that the deterioration of the frequency characteristics due to the P-type auto-doped layer formed near the interface between the P-type base layer and the N-type collector layer notably occurs especially in the semiconductor device having the N-type collector layer which has the relatively low impurity concentration requiring a high breakdown voltage. Conventionally, there has been a problem that the impurity concentration of the N-type collector layer cannot be set to be relatively low in order to prevent the deterioration of the frequency characteristics due to the P-type auto-doped layer so that a breakdown voltage cannot be improved.
Further, in the case of adding Ge to form the P-type base layer made of a SiGe layer at the time of epitaxially growing the base layer, it is possible to alleviate an energy barrier of hetero junction and to enhance the degree of movement of carriers, thereby improving the frequency characteristics. However, since the energy barrier occurs between the P-type auto-doped layer and the N-type collector layer as a result of forming the P-type auto-doped layer 1301, there is a problem that when the base layer is formed by using Ge, the width of the base layer is substantially widened so that the base traveling time is increased to reduce implantation efficiency and the frequency characteristics are further deteriorated.